Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
As a key player in the Design Verification team, you will architect the state of art verification environment to verify the industry's most advanced DSP design against reference Matlab/C models. You will closely work with architects, design, and verification lead to define and implement verification flow and methodology to verify the DSP complex in Aeva’s 4D Lidar Processing Chip. This is a great opportunity to work on the world's first 4D Lidar Chip!
What you'll do:
- Architect and implement state of art constrained random verification environment and testbench to verify the industry's most advanced DSP design against reference Matlab/C models
- Use, modify, and integrate the reference Matlab/C models in the simulation environment to verify the RTL using constrained random stimulus Verify DSP blocks against bit-accurate C-reference models
- Build reusable testbench to verify the DSP design target to ASIC, FPGA, and emulation platforms Define and execute verification plan for block, subsystem, and full-chip using SV/UVM methodology
- Identify and write functional coverage group to improve test/stimulus quality through coverage, analysis to identify verification gaps and achieve 100% coverage closure
- Work with the different stakeholders and functional leads to ensure high-quality DSP delivery on time
What you'll have:
- 8+ years of experience in design, verification, and validation of complex IPs, SOCs
- Strong experience in integrating and using Matlab/C-based models in a simulation environment
- Strong experience in building reusable and scalable constrained random verification environments from scratch
- Good understanding and working experience in DSP/Wifi Design is a big plus
- Create detailed test plans and write tests, run regressions, and collect coverage metrics to track verification progress and signoff
- Solid programming skills in SystemVerilog, UVM, C/C++, Perl/Python.
- Working experience and knowledge in AMBA AXI protocols, LPDDR, Ethernet, MIPI, high-speed serdes, etc.
- Proficient in debugging complex IP and SOC designs
- Excellent verbal and written communication skillsAbility to collaborate deeply with cross-functional leads and management teams
- Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement
Nice to haves:
- Developing Matlab/C reference model
- Experience in DSP/Wifi algorithm
- Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
- Post-silicon bring-up and validation planning and execution
What's in it for you:
- Be part of a fast-paced and dynamic team
- Very competitive compensation and meaningful equity
- Exceptional benefits: Medical, Dental, Vision, and more
- Unlimited PTO: We care about results, not punching timecards