Senior Hardware Verification Engineer

Mountain View, CA or Rochester, NY
About us:
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions. 

Role Overview:
We are looking for a senior-level Verification Engineer with deep expertise in ASIC / FPGA verification.

What you'll be doing

  • Help define a comprehensive verification methodology for SoCs, including test plan development and review, coverage goals, performance enhancements, and regression methodology.
  • Develop UVM components for stimulus generation and checking.
  • Create and execute a test plan including test writing and debugging at SoC or block level.
  • Leverage and refine automated build and regression flows for complex logic designs.
  • Report and summarize results to team leads.
  • Evaluate tradeoffs in block and full-chip verification, directed and constrained random approaches in a fast-paced startup environment.
  • Verify DSP blocks against bit-accurate C models.
  • Work closely with the algorithm team to identify corner cases.
  • Work closely with design engineers to understand functional safety requirements and how they influence verification.
  • Share domain expertise in verification techniques with other verification and design engineers

What you have

  • 7+  years industry experience; including at least one ASIC tapeout.
  • Extensive experience with a variety of verification tools and environments, and a deep understanding of their differences and capabilities to optimize the right methodology with schedules as the top priority.
  • Proven experience in full chip verification from test plan development to tape-out sign-off.
  • Experienced in SystemVerilog, UVM, and scripting languages like Python and Tcl.
  • Expertise in using industry standard simulation tools such as NC Verilog, VCS, Questa, etc.
  • Experience with gate simulations tape-out sign-off criteria.
  • Ability to debug/RCA large designs (needle in a haystack scenarios) comfortably.
  • Proven ability to deliver results in a very fast-moving startup environment, self-driven and a team player. 
  • Eager to learn & implement groundbreaking new hardware technology.
  • Knowledge of industry standards and VIP for AXI4, DDR, SPI, QSPI, ARM ISA, Ethernet, etc.  
  • Lab bringup and debug experience, including reproducing system level issues in simulations.

Nice-to-haves

  • Experience with Verilog DPI, C/C++ coding.
  • Experience with test plan building tools like Vmanager.
  • Experience with Verilog Real Number Modeling and mixed signal verification.
  • Experience with DFT verification.

What's in it for you

  • Be part of a fast paced and dynamic team
  • Very competitive compensation and meaningful stock grants
  • Exceptional benefits: Medical, Dental, Vision, and more
  • Unlimited PTO: We care about results, not punching timecards

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