Physical Design Engineer

Mountain View, CA
About us:
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions. 

Role Overview:
We are looking for an SoC Physical Design Engineer to work with our logic design team in handing off placed physical designs for back-end completion

What you'll be doing:

  • As a Physical Design Engineer, you’ll be responsible for performing synthesis, floorplanning, clock/power planning, timing analysis, ECOs, Library/tool flow setup, design QA, tapeout checklist, flow automation, etc.. on a high-performance Lidar Processing Chip.  You will work closely with logic designers and back-end engineers to ensure a high-quality handoff and minimize iteration in the implementation process.

What you'll have:

  • Broad knowledge of advanced synthesis techniques, Place and Route, floorplanning, global/local clock distribution, STA-based timing convergence, constraints management, power grid construction and analysis, low power implementation techniques, Statistical timing methods, formal equivalence checking, Physical Design Verification, and automated ECO flows.
  • In-depth knowledge of EDA tools used in physical design particularly Cadence.
  • Scripting expertise in Python, Tcl, PERL, etc..
  • Recent tapeouts in advanced technology nodes.
  • Ability to deliver results in a very fast-moving environment
  • Desire to learn & implement groundbreaking new hardware technology
  • Excellent communication and organization skills.

Nice to have

  • Familiarity with Verilog coding
  • Circuit design (Library, SRAM, IO) and/or signal integrity background
  • High-performance CPU or communication chip background.
  • Experience integrating high-performance analog in a high-performance digital chip.

What's in it for you:

  • Be part of an fast paced and dynamic team
  • Very competitive compensation and meaningful equity
  • Exceptional benefits: Medical, Dental, Vision, and more
  • Unlimited PTO: We care about results, not punching timecard

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