Design for Testability (DFT) Architect

Mountain View, CA
About us:
Aeva is building the next generation of sensing and perception for autonomous vehicles and beyond. With its unique ability to measure instantaneous velocity for each pixel, long-range performance at high resolutions, while being free from LiDAR or sunlight interference, Aeva’s 4D LiDAR is built from the ground up at silicon photonics scale for mass-market applications.

Role Overview:
We are looking for an SoC DFT Architect with experience in mixed-signal/high-performance digital DFT and Functional Safety. 

What you'll be doing:

  • As an SoC DFT Architect you’ll be responsible for defining and/or overseeing,  advanced design-for-test (DFT) methodologies for highly-complex digital and/or mixed-signal chips and/or IPs. You will have the opportunity to work with the rest of the team to document DFT specifications, and also develop DFT methodologies and infrastructure. In this role, you'll oversee the definition, development and verification of a consistent methodology for DFT across the whole SoC.

What you'll have:

  • 2-5 years’ experience writing RTL code in Verilog and/or VHDL
  • 2-5 years of verification experience
  • Broad domain knowledge of DFT including Scan/ATPG, MBiST, LBiST, JTAG, TAP, IO BiST, Analog BiST, etc..
  • In depth knowledge of EDA tools used in DFT.
  • Lab debug and DFT bringup experience
  • Ability to deliver results in a very fast-moving environment
  • Desire to learn & implement groundbreaking new hardware technology
  • Excellent communication and organization skills.


  • Functional Safety Experience

What's in it for you:

  • Be part of a fast paced and dynamic team
  • Very competitive compensation and meaningful stock grants
  • Exceptional benefits: Medical, Dental, Vision, and more
  • Unlimited PTO: We care about results, not punching timecards

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