Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
As a key player of the Design Verification team, you will lead and contribute to the verification of new breeds of SoC for advanced perception applications utilizing 4-D Lidar. You will architect and develop verification environments for block, subsystem, and full-chip using the state-of-art verification techniques, and verify complex SoC designs.
What you'll do:
- Lead and drive block, subsystems, and full-chip verification of 4D Lidar chips.
- Architect and build test benches, constrained random verification environments, reference models, and scoreboard using SystemVerilog and UVM methodologies
- Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to define the processes, methodology, and tools to verify complex SoCs.
- Define and execute verification plan for IP, block, subsystem, and full-chip using SystemVerilog/UVM methodology and C-based firmware running on the on-chip ARM processors
- Work with Architects, design and Verification, and System software teams to define system-level verification plans and prove that SOC meets the functional, performance, and power targets defined in the architecture and design specs.
- Identify and write functional coverage group to improve test/stimulus quality
- Through coverage, analysis to identify verification gaps and achieve 100% coverage closure
- Work with the different stakeholders and functional leads to ensure high-quality SoC delivery on time
What you'll have:
- 8+ years of experience in the design, verification, and validation of advanced ARM-based SOCs
- 5+ years in architecting and building constrained random verification environments, reference models, scoreboard, and directed self-checking tests using SystemVerilog and UVM methodologies
- Deep understanding of ARM-based SOC verification. Writing assembly and C/C++ diagnostic firmware for embedded ARM processors and debugging in a simulation environment
- Working experience and knowledge in AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, and high-speed serdes etc.
- Solid programming skills in SystemVerilog, UVM, C/C++, assembly, Perl/Python.
- Proficient in debugging complex SOC or CPU core designs
- Excellent verbal and written communication skills
- Ability to collaborate deeply with cross-functional leads and management teams
- Ability to deliver results in a very fast-moving environment
- Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement
Nice to haves:
- Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
- Post-silicon bring up and validation planning and execution
- Diagnostics Firmware development and validation
What's in it for you:
- Be part of a fast-paced and dynamic team
- Very competitive compensation and meaningful stock grants
- Exceptional beneﬁts: Medical, Dental, Vision, and more
- Unlimited PTO: We care about results, not punching time cards