ASIC Architect

Bangalore, India
About us:
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.

Role Summary:
As a key player on the Design team, you will lead the development of the Programmable Compute component (CPU, NOC, memory, and peripherals) for Aeva’s 4-D Lidar processing chip. You will be responsible for defining and leading the implementation of the SOC including all aspects of 3rd Party IP integration.

What you'll be doing:

  • Define, lead, and drive the development and integration of the sub-components of the Programmable Compute subsystem.  
  • Work with third-party IP providers including ARM and Arteris. 
  • Leading the team - comprehending and implementing applicable standards.
  • Implementing additional functionality including functional safety and robustness functions as per AEVA standards. 
  • Working in a dynamic and fast-paced startup environment and working closely with a team of passionate engineers to define the processes, methodology, and tools to verify complex SoCs.
  • Working with Architects, design engineers and verification engineers, and System software teams to define uArchitectures, and system-level verification plans to ensure that the system meets its functional, performance, and power targets. 

What you'll have:

  • 10+ years of experience in the design, verification, and validation of advanced ARM-based SOCs
  • Deep understanding of ARM CPUs.
  • Ability to achieve high performance and low power targets.
  • Experience in and knowledge of AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, and high-speed serdes.
  • Solid programming skills in SystemVerilog, Verilog, UVM, Perl/Python.
  • Proficiency in debugging complex SOC or CPU core designs
  • Excellent verbal and written communication skills with
  • a personal commitment to excellence in design documentation.
  • Ability to collaborate deeply with cross-functional leads and management teams
  • Ability to deliver results in a very fast-moving environment
  • Desire to learn & implement groundbreaking new processes and methodology for continuous improvement 

Nice to haves:

  • Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu 
  • Post-silicon bring-up and validation planning and execution experience
  • Diagnostics Firmware development and validation experience

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