Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
As a key player of the Design Verification team, you will architect and implement the reusable verification environment to verify the complex DSP design for Aeva’s 4D-Lidar Processing Chip. You will closely work with cross-functional leads to define and develop verification environments for block, subsystem, and full-chip using the constrained random verification techniques and verify complex DSP designs. This is a great opportunity to build reusable, scalable verification test benches from scratch to verify 4D-Lidar SOCs!
What you'll do:
- Architect and implement state of art constrained random verification environment and testbench to verify complex DSP systems in Lidar Processing Chips
- Build reusable testbench to verify the DSP design target to ASIC, FPGA, and emulation platform Built self-checking environment using Matlab/System-C-reference models and DPI flow
- Responsible for verifying DSP design at block, subsystems, and full-chip environments
- Verify DSP blocks against bit-accurate C-reference models
- Define and execute verification plan for IP, block, subsystem, and full-chip using SV/UVM methodology
- Identify and write functional coverage group to improve test/stimulus quality through coverage analysis to identify verification gaps and achieve 100% coverage closure
- Work with the different stakeholders and functional leads to ensure high-quality DSP delivery on time
What you'll have:
- 8+ years of experience in design, verification, and validation of complex IPs, SOCs
- Strong experience in building reusable and scalable constrained random verification environments from scratch
- 5+ years in architecting and building reusable and scalable constrained random verification environments to verify complex IPs/Blocks/SOCs from scratch
- Solid programming skills in SystemVerilog, UVM, C/C++, Perl/Python.
- Experience in verifying DSP design
- Working experience and knowledge in AMBA AXI protocols, LPDDR, Ethernet, MIPI, high-speed serdes, etc.
- Proficient in debugging complex IP and SOC designs
- Excellent verbal and written communication skillsAbility to collaborate deeply with cross-functional leads and management teams
- Ability to deliver results in a very fast-moving environment
- Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement
Nice to haves:
- Developing C/SystemC reference model
- Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
- Post-silicon bring-up and validation planning and execution
What's in it for you:
- Be part of a fast-paced and dynamic team
- Very competitive compensation and meaningful equity
- Exceptional benefits: Medical, Dental, Vision, and more
- Unlimited PTO: We care about results, not punching timecards