As a key player on the Design team, you will participate in the RTL design and development of the signal processing path for Aeva’s 4-D Lidar processing chip. You will be responsible for implementing and/or integrating sub-components of the design in FPGA.
What you'll be doing:
- Develop sub-components of the digital signaling pipeline.
- Code, Test, and Validate FPGA Aeva specific sub-components.
- Implement additional SOC functionality including functional safety and robustness functions.
- Focus on developing efficient, highly reliable, highly available, robust functionality.
- Work with Architects, design engineers and verification engineers, and System software teams to ensure that the SOC meets its functional, performance, and power targets.
What you'll have:
- 8+ years of experience in design and verification of advanced ARM-based SOCs
- Experience with ARM-based SOC design. Ability to achieve high performance and low power targets.
- Experience writing Verilog RTL Code.
- Working experience and knowledge in AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, and high-speed serdes.
- Proficient in debugging complex SOC or CPU core designs
- Excellent verbal and written communication skills
- Ability to collaborate deeply with cross-functional leads and management teams
- Ability to deliver results in a very fast-moving environment
- Desire to learn & implement groundbreaking new processes and methodology for continuous improvement
Nice to haves:
- Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
- Post-silicon bring-up and validation planning and execution
- Diagnostics Firmware development and validation