Director, Design Verification

Mountain View, CA
About us:
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Role Overview:
Aeva is seeking a hands-on Director of Design Verification. In this role, you will be responsible for the functional verification and validation of Aeva Digital ASICs.

What you'll do:

  • Manage SOC verification and validation teams, including recruiting and building team capabilities
  • Participate in the definition and deployment of industry-standard verification and validation methodologies
  • Drive strategy of verification testbench and test-plans in collaboration with design and architecture teams
  • Drive closure of functional verification including achieving functional coverage metrics in accordance with the verification plan
  • Drive validation strategy using FPGA prototyping or Emulation platforms working closely with cross-functional teams in the company
  • Drive closure of validation tasks to achieve pre-tapeout SOC and SW validation goals
  • Drive planning and execution of silicon bring-up activities, and be the focal point for resolving silicon issues in system validation
  • Collaborate with architects, designers, and SW engineers. Lead by example in a fast-paced environment.
  • Be a clear communicator with a proven ability to work across functions inside the company, and with partners across the globe.

What you'll have:

  • Strong management experience in building and guiding verification and validation engineers
  • Proven experience in state-of-the-art verification methodologies including SV/UVM, Coverage driven verification, and formal verification
  • Proven experience in developing test firmware for FPGA and/or Emulation platforms
  • Extensive experience in verification and validation of SOCs with LPDDR, Ethernet, and other standard interfaces, ARM/RISC-V processors
  • Must have worked with EDA vendors in the areas of simulation VIP, Emulation AVIP, and tools
  • BSEE, MSEE, or Ph.D. with 10+ years of relevant management experience in verification of Digital ASICs.

Nice to haves:

  • Working knowledge of verifying DSP sub-systems with reference models
  • Familiarity with verifying functional safety features (ISO 26262) in SOCs
  • Remote workforce (domestic and international) management experience

What's in it for you:

  • Be part of a fast-paced and dynamic team
  • Very competitive compensation and meaningful stock grants
  • Exceptional benefits: Medical, Dental, Vision, and more
  • Unlimited PTO: We care about results, not punching timecards

Salary Range

$227,200—$307,400 a year

Salary pay ranges are determined by role, level, and location. Within the range, the successful candidate’s starting base pay will be determined based on factors including job-related skills, experience, certifications, qualifications, relevant education or training, and market conditions. These ranges are subject to change in the future. Depending on the position offered, equity, bonus, and other forms of compensation may be provided as part of a total compensation package, in addition to comprehensive medical, dental, and vision coverage, pre-tax commuter and health care/dependent care accounts, 401k plan, life and disability benefits, flexible time off, paid parental leave, and 11 paid holidays annually.

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